The invention relates generally to a semiconductor memory device, and more particularly, to a method of fabricating a landing plug in a semiconductor memory device.
As the degree of integration of semiconductor memory devices has increased, a landing plug is used for electrical connection between an impurity region in a semiconductor substrate and a bit line and a storage node in the case of a Dynamic Random Access Memory (DRAM) device consisting of a transistor and a capacitor. In such a device, a conductive layer is filled in a space adjacent to the impurity region in the semiconductor substrate among spaces between word lines to form a the landing plug and a bit line contact and a storage node contact are formed so as to be connected to the landing plug.
More specifically with reference to FIG. 1, illustrating a DRAM device according to the prior art, a gate stack 120 is disposed on a semiconductor substrate 110 having an impurity region 112, such as a source/drain region. In the gate stack 120 structure, a gate insulation layer 121, a gate conductive layer 122, and a gate capping layer 123 are sequentially stacked. Insulating gate spacer layers 130 are disposed on side walls of the gate stack 120. A landing plug stack hole, by which the impurity region is exposed, is formed in a space between the gate spacer layers 130, and a landing plug 140 can be formed by filling the landing plug contact hole with a polysilicon layer. Such a landing plug 140 is connected to a conductive contact 160 thereabove, which passes through an insulation layer 150. In a DRAM device, this conductive contact 160 is a bit line contact or a storage node contact connected to a capacitor.
The landing plug 140 functions to pass electrical signals between the impurity region 112 therebelow and the conductive contact 160 thereabove. Therefore, to perform such a function, the landing plug 140 is generally formed of a polysilicon layer doped with impurity ions. However, due to a doping concentration of the landing plug 140, a trade-off relationship is established between leakage current properties and resistance properties of the device. Specifically, when the doping concentration of the landing plug 140 is low, resistance inside the landing plug 140 is increased and thus the signal transfer speed between the impurity region 112 and the conductive contact 160 is decreased. When the doping concentration of the landing plug 140 is raised to prevent this phenomenon, the impurity ions inside the landing plug 140 diffuse to the impurity region 112 to increase the intensity of an electric field applied to the impurity region and thus the amount of leakage current in the impurity region 112 increases.
Therefore, to solve these problems, an additional ion implantation process for increasing the doping concentration in only an upper portion of the landing plug 140 has been conventionally performed. According to this procedure, by increasing the doping concentration in the uppermost portion of the landing plug 140 through the additional ion implantation, it is possible to obtain an effect wherein an overall doping concentration of the landing plug 140 is increased while diffusion of the impurity ions into the impurity region 112 is minimized. However, such a method has the disadvantage that the number of process steps is increased and thus fabrication cost is increased, since an ion implantation process is additionally required.